This value is made available to the handler in the Exception Syndrome Register.
再细分
0 to 2^24-1 (a 24-bit value) in an ARM instruction
0-255 (an 8-bit value) in a 16-bit Thumb instruction
用法
The SVC instruction causes an exception. This means that the processor mode changes to Supervisor, the CPSR is saved to the Supervisor mode SPSR, and execution branches to the SVC vector
imm is ignored by the processor. However, it can be retrieved by the exception handler to determine what service is being requested.
底层细节
ARM指令编码
bit[31-28]: cond = condition field
bit[27-25]: op1 = oprand 1 ?
op1= 11b => Coprocessor and Supervisor Call == 协处理器和SVC